In general, the present invention relates to an information processing apparatus. More particularly, the present invention relates to an information processing apparatus wherein a device connected to a host computer by an ATA (AT Attachment) bus or by an ATAPI (ATA Packet Interface) bus controls its operating state to a sleep (half halted) state in accordance with a judgment made by the device itself, and the device is restored to its original operating state by a hardware reset signal received from the host computer.
A technology for putting an inform processing apparatus connected by an ATA bus or an ATAPI bus in a sleep mode in accordance with the operating state of the information processing apparatus has generally been becoming popular.
ATA is the name of an official standard of the IDE (Integrated Drive Electronics) standardized by the ANSI (American National Standards Institute). Much like the SCSI (Small Computer System Interface) standard, the ATA standard is also extended sequentially into ATA-2 and ATA-3 standards.
The ATAPI is a packet interface that is devised for connecting a device other than a hard disc to an IDE controller. An example of the device other than a hard disc is a CD-ROM. At the present time, there also exists an ATA-4 standard, which is a combination of the ATA standard and the ATAPI.
In addition, in the ATA standard and the ATAPI, there are also a plurality of standards such as those for 40, 44, 68 and 80 signal lines.
In the conventional system, a CPU (Central Processing Unit) employed in a personal computer issues a variety of commands to devices by way of an ATA or ATAPI command data interface to control the operation of the device. Referred to hereafter as a host computer, the personal computer is a host computer mounted on a motherboard. The devices include a CD-ROM (Compact Disc Read Only Memory) drive and a-hard disc drive, which are controlled by the commands issued by the CPU employed in the host computer. The ATA or ATAPI command data interface is referred to hereafter as an ATA/ATAPI command data interface.
Assume that a hard disc drive is employed as the device cited above. In this case, the CPU employed in the host computer changes the operating state to a half halted state called a sleep mode when there is no data exchanged with the hard disc drive for a period of time exceeding a predetermined time. In the sleep mode, the rotation of a motor employed in the device is stopped to reduce power consumption of the device.
In the configuration described above, however, only the power of the motor is reduced, and supplying of power to other control and interface components is continued. Thus, in order to further reduce the power consumption, the supplying of power to the other control and interface components must also be stopped as well. Since the device is controlled by the CPU employed in the host computer, however, it is necessary to stop the supplying of power to the ATA/ATAPI command data interface of the device and the supplying of power to a clock generator for supplying a clock signal to the ATA/ATAPI command data interface in order to further reduce the power consumption. If the supplying of power to the ATA/ATAPI command data interface of the device and the supplying of power to the clock generator are halted, however, a command issued by the CPU employed in the host computer can no longer be received. In consequence, in accordance with the device""s own judgment, the device is not capable of transiting to a sleep mode in which the supplying of power to the ATA/ATAPI command data interface of the device, the supplying of power to the clock generator and the supplying power to other components are halted. As a result, a command issued by the CPU employed in the host computer can only halt the motor so that there is raised a problem of an inability to reduce power adequately.
In addition, assume for example that a CPU employed in the device halts the supplying of power to the ATA/ATAPI command data interface in accordance with the CPU""s own judgment, entering a sleep mode. In this case, even though the power consumption can be reduced, in the sleep mode, a command issued by the CPU employed in the host computer cannot be received. As a result, there is raised a problem that it is impossible to restore the device from the sleep mode to the normal state.
It is thus an object of the present invention addressing the problems described above to provide a device connected to a central processing unit employed in a host computer through the ATA/ATAPI bus with a capability of entering a sleep mode in accordance with the device""s own judgment and returning to an original state in accordance with a hardware reset signal received from the central processing unit employed in the host computer.
An information processing apparatus provided by the present invention is characterized in that the information processing apparatus comprises: a state control unit for controlling the operation of the information processing apparatus to transit to a half halted state when no data is exchanged with a host computer through an ATA or ATAPI bus for at least a predetermined period of time; an interface processing unit for carrying out interface processing on a signal exchanged with the host computer through the ATA or ATAPI bus; and a reset signal supply means for passing on a received reset signal output by the host computer to make a request for termination of the half halted state to the state control unit directly from the ATA or ATAPI bus without passing through the interface processing unit when the state control unit controls the operation of the information processing apparatus to transit to the half halted state, wherein the state control unit restores the operation of the information processing apparatus from the half halted state to a normal state in accordance with the reset signal.
The information processing apparatus can be further provided with a clock generator for supplying a clock signal to the state control unit and the interface processing unit. When no data is exchanged with the host computer through the ATA or ATAPI bus for at least a predetermined period of time, the state control unit can drive the clock generator to supply a clock signal having a frequency lower than that of the normal clock signal only to the state control unit itself in order to control the operation of the information processing apparatus to transit to a half halted state.
The information processing apparatus can be further provided with a power supplying means for supplying power to the state control unit, the interface processing unit and the clock generator. When no data is exchanged with a CPU of the host computer through the ATA or ATAPI bus for at least a predetermined period of time, the state control unit can drive the clock generator to supply a clock signal having a frequency lower than that of the normal clock signal only to the state control unit itself, and can drive the power supplying means to supply power only to the state control unit itself and the clock generator in order to control the operation of the information processing apparatus to transit to a half halted state.
The reset signal may be implemented by a hardware reset signal conforming to ATA or ATAPI specifications.
The reset signal supply means can pass on a received hardware reset signal, which conforms to the ATA or ATAPI specifications and is output by the host computer to make a request for termination of the half halted state, as an IRQ signal to the state control unit directly from the ATA or ATAPI bus without passing through the interface processing unit when the state control unit controls the operation of the information processing apparatus to transit to a half halted state.
An information processing method provided by the present invention is characterized in that the information processing method including the reset signal supply step of passing on a received reset signal output by a host computer to make a request for termination of a half halted state to a state control unit directly from an ATA or ATAPI bus without passing through an interface processing unit when the state control unit controls a whole operation to transit to the half halted state, whereby the state control unit restores the operation of the information processing apparatus from the half halted state to a normal state in accordance with the reset signal.
In the information processing apparatus and the information processing method, which are provided by the present invention, the operation of the information processing apparatus is controlled to transit to a half halted state when no data is exchanged with a host computer through an ATA or ATAPI bus for at least a predetermined period of time; a signal exchanged with the host computer through the ATA or ATAPI bus is subjected to interface processing; a received reset signal output by the host computer to make a request for termination of the half halted state is passed on to a state control unit directly from the ATA or ATAPI bus without passing through an interface processing unit when the state control unit controls the operation of the information processing apparatus to transit to the half halted state; and the state control unit restores the operation of the information processing apparatus from the half halted state to a normal state in accordance with the reset signal.